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integrated silicon solution, inc. 1 rev. 0a 03/24/2014 copyright ? 2014 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason - ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is43r83200f is43/46r16160f, is43/46r32800f features ? vdd and vddq: 2.5v 0.2v ? sstl_2 compatible i/o ? double-data rate architecture; two data transfers per clock cycle ? bidirectional, data strobe (dqs) is transmitted/ received with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and centre-aligned with data for writes ? differential clock inputs (ck and ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? four internal banks for concurrent operation ? data mask for write data. dm masks write data at both rising and falling edges of data strobe ? burst length: 2, 4 and 8 ? burst type: sequential and interleave mode ? programmable cas latency: 2, 2.5 and 3 ? auto refresh and self refresh modes ? auto precharge ? t ras lockout supported (t rap = t rcd ) options ? confguration(s): 8mx32, 16mx16, 32mx8 ? package(s): 144 ball bga (x32) 66-pin tsop-ii (x8, x16) and 60 ball bga (x8, x16) ? lead-free package available ? temperature range: commercial (0c to +70c) industrial (-40c to +85c) automotive, a1 (-40c to +85c) automotive, a2 (-40c to +105c) 8mx32, 16mx16, 32mx8 256mb ddr sdram preliminary information march 2014 device overview issis 256-mbit ddr sdram achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle. the 268,435,456-bit memory array is internally organized as four banks of 64mb to allow concurrent operations. the pipeline allows read and write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. the programmable features of burst length, burst sequence and cas latency enable further advantages. the device is available in 8-bit, 16-bit and 32-bit data word size input data is registered on the i/o pins on both edges of data strobe signal(s), while output data is referenced to both edges of data strobe and both edges of clk. commands are registered on the positive edges of clk. an auto refresh mode is provided, along with a self refresh mode. all i/os are sstl_2 compatible. key timing parameters speed grade -5 -6 units f ck max cl = 3 200 167 mhz f ck max cl = 2.5 167 167 mhz f ck max cl = 2 133 133 mhz address table parameter 8m x 32 16m x 16 32m x 8 confguration 2m x 32 x 4 banks 4m x 16 x 4 banks 8m x 8 x 4 banks bank address pins ba0, ba1 ba0, ba1 ba0, ba1 autoprecharge pins a8/ap a10/ap a10/ap row address 4k(a0 C a11) 8k(a0 C a12) 8k(a0 C a12) column address 512(a0 C a7, a9) 512(a0 C a8) 1k(a0 C a9) refresh count com./ind./a1 a2 4k / 64ms 4k / 16ms 8k / 64ms 8k / 16ms 8k / 64ms
2 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f ck ck cke cs ras cas we a11 command decoder & clock genera to r mode registers and ext. mode registers refresh contr oller refresh counter self refresh contr oller ro w address la tch mul tiplexer column address la tch burst counter column address buffer column decoder d ata in buffer d ata out buffer i/o 0-31 v dd /v ddq v ss /v ss q 12 14 12 9 12 12 2 12 9 32 32 32 32 512 (x 32) 4096 4096 4096 ro w decoder 4096 memor y cell arra y b ank 0 sense amp i/o ga te bank contr ol logic ro w address buffer a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba0 ba1 a10 4 dm0-dm3 dqs0-dqs3 4 2 functional block diagram ( x 32 )
integrated silicon solution, inc. 3 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f functional block diagram ( x 16 ) ck ck cke cs ras cas we a12 a11 command decoder & clock genera to r mode registers and ext. mode registers refresh contr oller refresh counter self refresh contr oller ro w address la tch mul tiplexer column address la tch burst counter column address buffer column decoder d ata in buffer d ata out buffer i/o 0-15 v dd /v ddq v ss /v ss q 13 15 13 9 13 13 2 13 9 16 16 16 16 512 (x 16) 8192 8192 8192 ro w decoder 8192 memor y cell arra y b ank 0 sense amp i/o ga te bank contr ol logic ro w address buffer a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba0 ba1 a10 2 ldm, udm ldqs , udqs 2 2
4 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f pin configurations 66 pin tsop - type ii for x8 v dd dq0 v dd q nc dq1 v ss q nc dq2 v dd q nc dq3 v ss q nc nc v ddq nc nc vdd nc nc we cas ras cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ss dq7 v ss q nc dq6 v dd q nc dq5 v ss q nc dq4 v dd q nc nc v ssq dqs nc vref vss dm ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss pin description: x8 a0-a12 row address input a0-a9 column address input ba0, ba1 bank select address dq0 C dq7 data i/o ck, system clock input cke clock enable chip select cas column address strobe command as row address strobe command w write enable dm data write mask dqs data strobe vdd power vddq power supply for i/o pins vss ground vssq ground for i/o pins vref sstl_2 reference voltage nc no connection
integrated silicon solution, inc. 5 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f pin configuration package code b: 60-ball fbga (top view) for x8 (8mm x 13mm body, 0.8mm ball pitch) top view (balls seen through the package) pin description: x8 a0-a12 row address input a0-a9 column address input ba0, ba1 bank select address dq0 C dq7 data i/o ck, ck system clock input cke clock enable cs chip select cas column address strobe command ras row address strobe command we write enable dm data write mask dqs data strobe vdd power vddq power supply for i/o pins vss ground vssq ground for i/o pins vref sstl_2 reference voltage nc no connection a b c d e f g h j k l m vssq dq 7 nc nc nc nc vddq dq6 vddq nc nc nc vssq vd dd q0 dq 1n c vddq dq2 dq3 vssq nc nc vddq vd d we ca s ra s ba1 ba0 a0 a1 0/ ap a2 a1 a5 a6 a7 a8 a9 cs vref a12 nc a4 a3 dq5 vddq vssq dq4 ck e a1 1 ck vssq dqs vss dm ck vss vd d vss 12 37 89 x8 devi ce bal lp attern a b c d e f g h j k l m :b al le xist ing :d e populate db al l to pv ie w (see th eb a lls through th ep ac k age) 12 3 456 789 bga package ball pattern top view
6 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f pin configurations 66 pin tsop - type ii for x16 v dd dq0 v dd q dq1 dq2 v ss q dq3 dq4 v dd q dq5 dq6 v ss q dq7 nc v ddq ldqs nc vdd nc ldm we cas ras cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ssq udqs nc vref vss udm ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss pin description: x16 a0-a12 row address input a0-a8 column address input ba0, ba1 bank select address dq0 C dq15 data i/o ck, ck system clock input cke clock enable cs chip select cas column address strobe command ras row address strobe command we write enable ldm, udm data write mask ldqs, udqs data strobe vdd power vddq power supply for i/o pins vss ground vssq ground for i/o pins vref sstl_2 reference voltage nc no connection
integrated silicon solution, inc. 7 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f pin configuration package code b: 60-ball fbga (top view) for x16 (8mm x 13mm body, 0.8mm ball pitch) top view (balls seen through the package) pin description: x16 a0-a12 row address input a0-a8 column address input ba0, ba1 bank select address dq0 C dq15 data i/o ck, ck system clock input cke clock enable cs chip select cas column address strobe command ras row address strobe command we write enable ldm, udm data write mask ldqs, udqs data strobe vdd power vddq power supply for i/o pins vss ground vssq ground for i/o pins vref sstl_2 reference voltage nc no connection a b c d e f g h j k l m vssq dq 15 dq14 vddq dq13 dq12 vddq dq3 vssq vd dd q0 dq 2d q1 vddq dq4 dq6 vssq dq 5 ld qs dq 7 vddq ld mv dd we ca s ra s ba1 ba0 a0 a1 0/ ap a2 a1 a5 a6 a7 a8 a9 cs vref a12 nc a4 a3 dq11 vddq vssq dq9 dq10 dq8 ck e a1 1 ck vssq udqs vss udm ck vss vd d vss 12 37 89 x1 6d evic e bal lp attern a b c d e f g h j k l m :b al le xist ing :d e populate db al l to pv ie w (see th eb a lls through th ep ac k age) 12 3 456 789 bga package ball pattern top view
8 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f a b c d e f g h j k l m dqs0 dq4 dq6 dq7 dq17 dq19 dqs2 dq21 dq22 cas ras cs dm0 vddq dq5 vddq dq16 dq18 dm2 dq20 dq23 we nc nc vssq nc vssq vdd vddq vddq nc vddq vddq vdd nc ba0 dq3 vddq vssq vss vssq vssq vssq vssq vssq vss ba1 a0 dq2 dq1 vssq vssq vss vss vss vss vss a10 a2 a1 dq0 vddq vdd vss vss vss vss vss vss vdd a11 a3 dq31 vddq vdd vss vss vss vss vss vss vdd a9 a4 dq29 dq30 vssq vssq vss vss vss vss vss nc a5 a6 dq28 vddq vssq vss vssq vssq vssq vssq vssq vss nc a7 vssq nc vssq vdd vddq vddq nc vddq vddq vdd ck a8 dm3 vddq dq26 vddq dq15 dq13 dm1 dq11 dq9 nc ck cke dqs3 dq27 dq25 dq24 dq14 dq12 dqs1 dq10 dq8 nc nc vref 1 2 3 4 5 6 7 8 9 10 11 12 note: vss balls inside the dotted box are optional for purposes of thermal dissipation. a0-a11 row address input a0-a7, a9 column address input ba0, ba1 bank select address dq0 C dq31 data i/o ck, ck system clock input cke clock enable cs chip select cas column address strobe command ras row address strobe command we write enable dm0-dm3 data write mask dqs0-dqs3 data strobe vdd power vddq power supply for i/o pins vref sstl_2 reference voltage vss ground vssq ground for i/o pins nc no connection pin description: for x32 pin configuration package code b: 144-ball fbga (top view) (12mm x 12mm body, 0.8mm ball pitch) top view (balls seen through the package)
integrated silicon solution, inc. 9 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f pin functional descriptions symbol type description ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck. input and output data is referenced to the crossing of ck and ck (both directions of crossing). internal clock signals are derived from ck/ ck. cke input clock enable: cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active powerdown (row active in any bank). cke is synchronous for all functions except for self refresh exit, which is achieved asynchronously. input buffers, excluding ck, ck and cke, are disabled during power-down and self refresh mode which are contrived for low standby power consumption. cs input chip select: cs enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras, cas, we input command inputs: ras, cas and we (along with cs) defne the command being entered. dm: x8; ldm, udm: x16; dm0-dm3: x32 input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading matches the dq and dqs loading. for x16 devices, ldm corresponds to the data on dq0-dq7, udm corresponds to the data on dq8-dq15. for x32 devices, dm0 corresponds to the data on dq0-dq7, dm1 corresponds to the data on dq8-dq15, dm2 corresponds to the data on dq16-dq23, and dm3 corresponds to the data on dq24-dq31. ba0, ba1 input input bank address inputs: ba0 and ba1 defne to which bank an active, read, write or precharge command is being applied. a [12:0] input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read / write commands, to select one location out of the memory array in the respective bank. the address inputs also provide the opcode during a mode register set command. a12 is not used for x32. dq: dq0-dq7: x8; dq0-dq15: x16 dq0-dq31: x32 i/o data bus: input / output dqs: x8: ldqs, udqs x16: dqs0-dqs3: x32 i/o data strobe: output with read data, input with write data. edge-aligned with read data, centered with write data. used to capture write data. for x16 device, ldqs corresponds to the data on dq0-dq7, udqs corresponds to the data on dq8-dq15. for x32 device, dqs0 corresponds to the data on dq0-dq7, dqs1 corresponds to the data on dq8-dq15, dqs2 corresponds to the data on dq16-dq23, and dqs3 corresponds to the data on dq24-dq31. nc -- no connect: should be left unconnected. vref supply sstl_2 reference voltage. vddq supply i/o power supply. vssq supply i/o ground. vdd supply power supply. vss supply ground.
10 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f commands truth tables all commands (address and control signals) are registered on the positive edge of clock (crossing of ck going high and ck going low). truth table shows basic timing parameters for all commands. name (function) cs ras cas we ba ap address notes deselect (nop) h x x x x x x 2 no operation (nop) l h h h x x x 2 active (select bank and activate row) l l h h valid x row read (select bank and column and start read burst) l h l h valid l column read with ap (read burst with auto precharge) l h l h valid h column 3 write (select bank and column and start write burst) l h l l valid l column write with ap (write burst with auto precharge) l h l l valid h column 3 burst terminate l h h l x x x 4 precharge (deactivate row in selected bank) l l h l valid l x 5 precharge all (deactivate rows in all banks) l l h l x h x 5 auto refresh or enter self refresh l l l h x x x 6,7,8 mode register set l l l l valid op-code 9 notes: 1. all states and sequences not shown are illegal or reserved. 2. deselect and nop are functionally interchangeable. 3. autoprecharge is non-persistent. ap high enables auto precharge, while ap low disables autoprecharge. 4. burst terminate applies to only read bursts with auto precharge disabled. this command is undefned and should not be used for read with auto precharge enabled, and for write bursts. 5. if ap is low, bank address determines which bank is to be precharged. if ap is high, all banks are precharged and ba0- ba1are dont care. 6. this command is auto refresh if cke is high, and self refresh if cke is low. 7. all address inputs and i/o are don't care except for cke. internal refresh counters control bank and row addressing. 8. all banks must be precharged before issuing an auto-refresh or self refresh command. 9. ba0 and ba1 value select between mrs and emrs. 10. cke is high for all commands shown except self refresh. truth table - dm operations function dm dq write enable l valid write inhibit h x note: used to mask write data, provided coincident with the corresponding data. truth table - commands x32 x16 x8 auto precharge (ap) a8 a10 a10 row address (ra) a0-a11 a0-a12 a0-a12 column address (ca) a0-a7, a9 a0-a8 a0-a9 addressing
integrated silicon solution, inc. 11 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f addressing truth table - cke cke n-1 cke n current state command n action n notes l l power down x maintain power down l l self refresh x maintain self refresh l h power down nop or deselect exit power down 6 l h self refresh nop or deselect exit self refresh 6, 7 h l all banks idle nop or deselect precharge power down entry 6 h l bank(s) active nop or deselect active power down entry 6 h l all banks idle auto refresh self refresh entry h h see truth tables - commands notes: 1. cken is the logic state of cke at clock edge n; cken-1 was the state of cke at the previous clock edge. 2. current state is the state of ddr immediately prior to clock edge n. 3. commandn is the command registered at clock edge n, and actionn is the result of commandn. 4. all states and sequences not shown are illegal or reserved. 5. cke must not go low during a read or write, and must stay high until after t rpst or t wr , respectively. 6. deselect and nop are functionally interchangeable. 7. nops or deselects must be issued for at least t snr after self-refresh exit before any other command. after dll reset, at least t xsrd must elapse before any read commands occur. basic timing parameters for commands note: input = a0 - an, ba0, ba1, cke, cs , ras , cas , we ; an = address bus msb = don' t ca re t cl t ch t is t ih t ck ck ck i nput va li d va li d va li d
12 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f simplified state diagram preall = precharge all banks ckel = enter power down mrs = mode register set ckeh = exit power down emrs = extended mode register set act = active se lf au to idl e mr s em rs ro w pr ec har ge wr it e wr it e wr it e read read po we r ac t read a read re fs re fs x re fa c kel mr s c keh c keh c kel wr it e po we r ap p lie d automati cs equenc e command sequenc e read a wr it ea read pr e pr e pr e pr e refr es h refr es h ac ti ve ac ti ve po we r down pr ec har ge po we r down on a read a read a wr it ea bu rs ts to p pr eal l pr ec har ge pr eal l refs = enter self refresh write a = write with autoprecharge refsx = exit self refresh read a = read with autoprecharge refa = auto refresh pre = precharge
integrated silicon solution, inc. 13 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f functional description the ddr sdram is a high speed cmos, dynamic random-access memory internally confgured as a quad-bank dram. the 256mb devices contains: 268,435,456 bits. the ddr sdram uses double data rate architecture to achieve high speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and the row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. prior to normal operation, the ddr sdram must be initialized. the following section provides detailed information covering device initialization, register defnition, command description and device operation initialization ddr sdrams must be powered up and initialized in a predefned manner. operations procedures other than those specifed may result in undefned operation. if there is any interruption to the device power, the initialization routine should be followed. the steps to be followed for device initialization are listed below. the initialization flow diagram and the initialization flow sequence are shown in the following fgures. the mode register and extended mode register do not have default values. if they are not programmed during the initialization sequence, it may lead to unspecifed operation. the clock stop feature is not available until the device has been properly initialized from step 1 through 13. ? step 1: apply vdd before or at the same time as vddq. ? step 2: cke must maintain lvcmos low until vref is stable. apply vddq before applying vtt and vref. ? step 3: there must be at least 200 s of valid clocks before any command may be given to the dram. during this time nop or deselect commands must be issued on the command bus and cke should be brought high. ? step 4: issue a precharge all command. ? step 5: provide nops or deselect commands for at least trp time. ? step 6: issue emrs command ? step 7: issue mrs command, load the base mode register and to reset the dll. set the desired operating modes. ? step 8: provide nops or deselect commands for at least tmrd time. ? step 9: issue a precharge all command ? step 10: issue 2 or more auto refresh cycles ? step 11: issue mrs command with the reset dll bit deactivated to program operating parameters without resetting the dll ? step 12: provide nop or deselect commands for at least tmrd time. ? step 13: the dram has been properly initialized and is ready for any valid command.
14 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f initialization waveform sequence notes: 1. vtt is not applied directly to the device, however tvtd must be greater than or equal to zero to avoid device latch--up. 2. tmrd is required before any command can be applied, and 200 cycles of ck are required before any executable command can be applied 3. the two auto refresh commands may be moved to follow the frst mrs but precede the second precharge all com- mand. 4. ap is a8 for x32, and a10 for x8/x16. address is a0 to a12 except ap. ck e lv cm os lo wl evel dq ba0, ba1 200c ycles of ck ** extended mode regi st er se t load mode regi st er , re se td ll (w it ha p= h) load mode regi st er (w it ha p= l) tmrd t mr d tmrd t rp trfc trfc t is po we r- -u p: vd d and cl ks tabl e t= 200 s hi gh-- z t ih ( ) ( ) ( ) ( ) dm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq s hi gh-- z ( ) ( ) ( ) ( ) a ddress ap 4 all banks do n? tc ar e ck ck t ck t ch t cl vt t ( syst em 1 ) vr ef vd d vd dq co mmand mr s nop pre emrs ar ) ar t is t ih ba0= h, ba1 =l t is ti h ti st ih ba0= l, ba1= l t is t ih ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )) ( ) ( ( ) code code ti st ih code c ode mr s ba0= l, ba1= l c ode c ode ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) pre all banks ti st ih ra ra act ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) tv dt 0 22 2
integrated silicon solution, inc. 15 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f mode register (mr) definition the mode register is used to defne the specifc mode of operation of the ddr sdram. this defnition includes the defnition of a burst length, a burst type, and a cas latency. the mode register is programmed via the mode register set command (with ba0=0 and ba1=0) and will retain the stored information until it is reprogrammed, or the device loses power. mode register bits a0-a2 specify the burst length, a3 the type of burst (sequential or interleave), a4-a6 the cas latency, and a8 dll reset. a logic 0 should be programmed to all the undefned addresses bits to ensure future compatibility. the mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specifed time tmrd before initiating any subsequent operation. violating either of these requirements will result in unspecifed operation. reserved states should not be used, as unknown operation or incompatibility with future versions may result mode register ba1 ba0 a12 1 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved address bus (ax) mode reg. (ex) a3 burst type 0 sequential 1 interleave a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 2.5 1 1 1 reserved notes: 1. a12 is not used in x32 and should be ignored for this option. 2. a logic 0 should be programmed to all unused / undefned address bits to ensure future compatibility. ba1 ba0 mode register defnition 0 0 program mode register 0 1 program extended mode register 1 0 reserved 1 1 reserved a12 a11 a10 a9 a8 a7 dll 0 0 0 0 0 0 normal operation 0 0 0 0 1 0 reset dll
16 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being set and the burst order as in burst defnition. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. notes: 1. for a burst length of two, a1-an selects the two data element block; a0 selects the frst access within the block. 2. for a burst length of four, a2-an selects the four data element block; a0-a1 selects the frst access within the block. 3. for a burst length of eight, a3-an selects the eight data element block; a0-a2 selects the frst access within the block. 4. whenever a boundary of the block is reached within a given sequence, the following access wraps within the block. b urst definition burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 0 0-1 0-1 1 1-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
integrated silicon solution, inc. 17 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-an when the burst length is set to two, by a2-an when the burst length is set to 4, by a3-an when the burst length is set to 8. an is the most signifcant column address bit, which depends if the device is x8, x16 or x32. an = a9 for x8, an = a8 for x16 and an = a9 for x32. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address. read latency the read latency, or cas latency, is the delay between the registration of a read command and the availability of the frst piece of output data. if a read command is registered at a clock edge n and the latency is 3 clocks, the frst data element will be valid at n + 2tck + tac. if a read command is registered at a clock edge n and the latency is 2 clocks, the frst data element will be valid at n + tck + tac. operating mode the normal operating mode is selected by issuing a mode register set command with bits a7 to an each set to zero, and bits a0 to a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9 to an each set to zero, bit a8 set to one, and bits a0 to a6 set to the desired values. a mode register set command issued to reset the dll must always be followed by a mode register set command to select normal operating mode (a8=0). all other combinations of values for a7 to an are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
18 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f cas latencies
integrated silicon solution, inc. 19 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f extended mode register (emr) definition the extended mode register controls functions beyond those controlled by the mode register; these additional functions include dll enable/disable, and output drive strength selection. the extended mode register is programmed via the mode register set command (with ba1=0 and ba0=1) and will retain the stored information until it is reprogrammed, or the device loses power. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specifed time tmrd before initiating any subsequent operation. violating either of these requirements will result in unspecifed operation. reserved states should not be used, as unknown operation or incompatibility with future versions may result. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization, and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation (upon exiting self refresh mode, the dll is enabled automatically). any time the dll is enabled a dll reset must follow and 200 clock cycles must occur before any executable command can be issued. output drive strength (ds) the normal drive strength for all outputs is specifed to be sstl_2, class ii. this dram also supports a reduced driver strength option, intended for lighter load and/or point-to-point environments. extended mode register ba1 ba0 a12 2 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a0 dll 0 enable 1 disable address bus (ax) ext. mode reg. (ex) a6 a1 drive strength 0 0 full (100%) 0 1 weak (60%) 1 0 reserved 1 1 matched (30%) notes: 1. a logic 0 should be programmed to all unused/undefned ad - dress bits to ensure future compatibility 2. a12 is not used for x32 and should be ignored for this option. ba1 ba0 mode register defnition 0 0 program mode register 0 1 program extended mode register 1 0 reserved 1 1 reserved reserved (1) reserved (1)
20 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f absolute maximum rating parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 3.6 v voltage on vdd & vddq supply relative to vss v dd , v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 o c power dissipation p d 1.5 w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommend operation condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability ac/dc electrical characteristics and operating conditions recommended operating conditions (voltage referenced to vss=0v; ta=0 to 70 o c for commercial, ta = -40 o c to +85 o c for industrial and a1, ta = -40 o c to +105 o c for a2) parameter symbol min max unit note supply voltage (with a nominal vdd of 2.5v) v dd 2.3 2.7 v i/o supply voltage (with a nominal vdd of 2.5v) v ddq 2.3 2.7 v i/o reference voltage v ref 0.49*vddq 0.51*vddq v 1 i/o termination voltage (system) v tt vref-0.04 vref+0.04 v 2 input logic high voltage v ih ( dc ) vref+0.15 vddq+0.3 v input logic low voltage v il ( dc ) -0.3 vref-0.15 v input voltage level, clk and clk inputs v in ( dc ) -0.3 vddq+0.3 v input differential voltage, clk and clk inputs v id ( dc ) 0.36 vddq+0.6 v 3 v-i matching: pullup to pulldown current ratio v i (ratio) 0.71 1.4 C 4 input leakage current i l -2 2 ua output leakage current i oz -5 5 ua output high current (normal strength driver) ; vout = vtt + 0.84v i oh -16.8 C ma output low current (normal strength driver) ; vout = vtt - 0.84v i ol 16.8 C ma output high current (half strength driver); vout = vtt + 0.45v i ohr -9 C ma output low current (half strength driver); vout = vtt - 0.45v i olr 9 C ma ambient operating temperature commercial industrial a1 a2 t a t a t a t a 0 -40 -40 -40 +70 +85 +85 +105 o c o c o c o c note : 1. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of same. peak-to peak noise on vref may not exceed +/-2% of the dc value. 2. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref 3. vid is the magnitude of the difference between the input level on clk and the input level on clk. 4. the ratio of the pullup current to the pulldown current is specifed for the same temperature and voltage, over the entire tem- perature and voltage range, for device drain to source voltages from 0.25v to 1.0v. for a given output, it represents the maxi- mum difference between pullup and pulldown drivers due to process variation. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
integrated silicon solution, inc. 21 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f capacitance characteristics (1, 2) (v dd = v ddq = 2.5v + 0.2v, unless otherwise noted) symbol parameter test condition limits units min max ci(a) input capacitance, address pin vi=1.25v f=100mhz vi=25mvrms 1.3 3 pf ci(c) input capacitance, control pin 1.3 3 pf ci(k) input capacitance, clk pin 2 4 pf ci/o i/o capacitance, i/o, dqs, dm pin 3 5 pf notes: 1. this parameter is characterized. 2. conditions: frequency = 100mhz; v out (dc) = v dd /2; v out (peak-to-peak) = 0.2v; v ref = vss. package substrate theta-ja (airfow = 0m/s) theta-ja (airfow = 1m/s) theta-ja (airfow = 2m/s) theta-jc units tsop2(66) 4-layer 73.3 66.3 62.4 12.2 c/w bga(60) 4-layer 40.1 36.5 34.2 7.9 c/w bga(144) 4-layer 29.4 29 27.1 4.5 c/w thermal resistance
22 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f idd specifcation parameters and test conditions: x8, x16 (v dd = v ddq = 2.5v 0.2v, vss = vssq = 0v, output open, unless otherwise noted) symbol parameter/ test condition -5 -6 units idd0 operating current for one bank active-precharge; trc = trc(min); tck = tck(min); dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; cs = high between valid commands. 120 120 ma idd1 operating current for one bank operation; one bank open, bl = 4, trc = trc(min), tck = tck(min), iout=0ma, address and control inputs changing once per clock cycle. 140 130 ma idd2p precharge power-down standby current; all banks idle; power-down mode; cke vil(max); tck = tck(min); vin = vref for dq, dqs and dm 40 40 ma idd2f precharge foating standby current; cs vih(min); all banks idle; cke vih(min); tck = tck(min); address and other control inputs changing once per clock cycle; vin = vref for dq, dqs and dm 100 100 ma idd3p active power-down standby current; one bank active; power-down mode; cke vil(max); tck = tck(min); vin = vref for dq, dqs and dm 40 40 ma idd3n active standby current; cs vih(min); cke vih(min); one bank active; trc = tras(max); tck = tck(min); dq, dqs and dm inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 100 100 ma idd4r operating current for burst read; burst length = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck = tck(min); 50% of data changing on every transfer; lout = 0ma 240 210 ma idd4w operating current for burst write; burst length = 2; writes; continuous burst; one bank active address and control inputs changing once per clock cycle; tck = tck(min); dq, dm and dqs inputs changing twice per clock cycle, 50% of input data changing at every transfer 260 220 ma idd5 auto refresh current; trc = trfc(min); 140 140 ma idd6 self refresh current; cke 0.2v; 6 6 ma idd7 operating current for four bank operation; four bank interleaving reads (bl=4) with auto precharge; trc = trc(min), tck = tck(min); address and control inputs change only during active, read, or write commands 280 280 ma
integrated silicon solution, inc. 23 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f idd specifcation parameters and test conditions: x32 (v dd = v ddq = 2.5v 0.2v, vss = vssq = 0v, output open, unless otherwise noted) symbol parameter/ test condition -5 -6 units idd0 operating current for one bank active-precharge; trc = trc(min); tck = tck(min); dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; cs = high between valid commands. 160 160 ma idd1 operating current for one bank operation; one bank open, bl = 4, trc = trc(min), tck = tck(min), iout=0ma, address and control inputs changing once per clock cycle. 190 170 ma idd2p precharge power-down standby current; all banks idle; power-down mode; cke vil(max); tck = tck(min); vin = vref for dq, dqs and dm 50 50 ma idd2f precharge foating standby current; cs vih(min); all banks idle; cke vih(min); tck = tck(min); address and other control inputs changing once per clock cycle; vin = vref for dq, dqs and dm 110 110 ma idd3p active power-down standby current; one bank active; power-down mode; cke vil(max); tck = tck(min); vin = vref for dq, dqs and dm 50 50 ma idd3n active standby current; cs vih(min); cke vih(min); one bank active; trc = tras(max); tck = tck(min); dq, dqs and dm inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 110 110 ma idd4r operating current for burst read; burst length = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck = tck(min); 50% of data changing on every transfer; lout = 0ma 330 300 ma idd4w operating current for burst write; burst length = 2; writes; continuous burst; one bank active address and control inputs changing once per clock cycle; tck = tck(min); dq, dm and dqs inputs changing twice per clock cycle, 50% of input data changing at every transfer 340 310 ma idd5 auto refresh current; trc = trfc(min); 220 220 ma idd6 self refresh current; cke 0.2v; 6 6 ma idd7 operating current for four bank operation; four bank interleaving reads (bl=4) with auto precharge; trc = trc(min), tck = tck(min); address and control inputs change only during active, read, or write commands 430 430 ma
24 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f parameter symbol -5 -6 units min max min max dq output access time for clk,/clk tac -0.7 0.7 -0.7 0.7 ns dqs output access time for clk,/clk tdqsck -0.6 0.6 -0.6 0.6 ns clk high-level width tch 0.45 0.55 0.45 0.55 tck clk low-level width tcl 0.45 0.55 0.45 0.55 tck clk half period thp min (tcl,tch) C min (tcl,tch) C ns clk cycle time cl=3 tck(3) 5 10 6 10 ns cl=2.5 tck(2.5) 6 10 6 10 ns cl=2 tck(2) 7.5 10 7.5 10 ns dq and dm input hold time tdh 0.4 C 0.45 C ns dq and dm input setup time tds 0.4 C 0.45 C ns control & address input pulse width (for each input) tipw 2.2 C 2.2 C ns dq and dm input pulse width (for each input) tdipw 1.75 C 1.75 C ns dq & dqs high-impedance time from clk,/clk thz C 0.7 C 0.7 ns dq & dqs low--impedance time from clk,/clk tlz -0.7 C -0.7 C ns dqs--dq skew, dqs to last dq valid, per group, per access tdqsq C 0.4 C 0.45 ns dq/dqs output hold time from dqs tqh thp-tqhs C thp- tqhs C ns data hold skew factor tqhs C 0.5 C 0.55 ns write command to frst dqs latching transition tdqss 0.72 1.28 0.75 1.28 tck dqs input high pulse width tdqsh 0.35 C 0.35 C tck dqs input low pulse width tdqsl 0.35 C 0.35 C tck dqs falling edge to clk setup time tdss 0.2 C 0.2 C tck dqs falling edge hold time from clk tdsh 0.2 C 0.2 C tck mode register set command cycle time tmrd 2 C 2 C tck write preamble setup time twpres 0 C 0 C ns write postamble twpst 0.4 0.6 0.4 0.6 tck write preamble twpre 0.25 C 0.25 C tck address and control input hold time (fast slew rate) tihf 0.6 C 0.75 C ns address and control input setup time (fast slew rate) tisf 0.6 C 0.75 C ns address and control input hold time (slow slew rate) tih 0.7 C 0.8 -C ns address and control input setup time (slow slew rate) tis 0.7 C 0.8 C ns read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck active to precharge command tras 40 70,000 42 120,000 ns ac timing requirements absolute specifcations (vdd, vddq = +2.5 v 0.2 v)
integrated silicon solution, inc. 25 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f parameter symbol -5 -6 units min max min max active to active/auto refresh command period trc 55 C 60 C ns auto refresh to active/auto trfc 70 C 72 C ns active to read or write delay trcd 15 C 15 C ns precharge command period trp 15 C 15 C ns active to autoprecharge delay trap 15 C 15 C ns active bank a to active bank b command trrd 10 C 12 C ns write recovery time twr 15 C 15 C ns auto precharge write recovery + precharge time tdal twr+trp C twr+trp C tck internal write to read command delay twtr 2 C 1 C tck exit self refresh to non-read txsnr 70 C 75 C ns exit self refresh to read command txsrd 200 C 200 C tck average periodic refresh interval (x8/x16) t a 85 oc trefi C 7.8 C 7.8 ms t a > 85 oc, a2 only trefi C 1.9 C 1.9 ms average periodic refresh interval (x32) t a 85 oc trefi C 15.6 C 15.6 ms t a > 85 oc, a2 only trefi C 3.9 C 3.9 ms ac timing requirements absolute specifcations (vdd, vddq = +2.5 v 0.2 v@-5/-6) output load condition dq output ti mi ng measurement re fe re n ce po in t v re f v re f dqs v out v re f 30 pf 50 v tt =v re f zo =5 0 ? ?
26 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f notes: 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifcations and device operation are guaranteed for the full voltage range specifed. 3. ac timing and idd tests may use a vil to vih swing of up to 1.5v in the test environment, but input timing is still referenced to vref (or to the crossing point for ck//ck), and parameter specifcations are guaranteed for the specifed ac input levels un- der normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between vil(ac) and vih(ac). 4. the ac and dc input level specifcations are as defned in the sstl_2 standard (i.e. the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 5. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on vref may not exceed +2% of the dc value. 6. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref. 7. vid is the magnitude of the difference between the input level on clk and the input level on /clk. 8. the value of vix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. 9. enables on-chip refresh and address counters. 10. idd specifcations are tested after the device is properly initialized. 11. this parameter is sampled. vddq = 2.5v+0.2v, vdd = 2.5v + 0.2v , f = 100 mhz, ta = 25c, vout(dc) = vddq/2, vout(peak to peak) = 25mv. dm inputs are grouped with i/o pins - refecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. the clk//clk input reference level (for timing referenced to clk//clk) is the point at which clk and /clk cross; the input reference level for signals other than clk//clk, is vref. 13. inputs are not recognized as valid until vref stabilizes. exception: during the period before vref stabilizes, cke< 0.3vddq is recognized as low. 14. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not refer- enced to a specifc voltage level, but specify when the device output is no longer driving (hz), or begins driving (lz). 15. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. the specifc requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defned as monotonic, and meeting the input slew rate specifcations of the device. when no writes were previously in progress on the bus, dqs will be transitioning from high-z to logic low. if a previous write was in prog- ress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 17. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 18. txprd should be 200 tclk in the condition of the unstable clk operation during the power down mode. 19. for command/address and ck & /ck slew rate > 1.0v/ns. 20. min (tcl,tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device. 21. for a2 temperature grade with t a > 85c: idd2f, idd3n, and idd7 are deregulated to 10% above these values; idd2p and idd6 are deregulated to 20% above these values.
integrated silicon solution, inc. 27 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f output slew rate characteristics slew rate characteristic typical range (v/ns) min (v/ns) max (v/ns) pullup slew rate 1.2-2.5 0.7 5.0 pulldown slew rate 1.2-2.5 0.7 5.0 ac overshoot/undershoot specification for address and control pins parameter max units peak amplitude allowed for overshoot 1.5 v peak amplitude allowed for undershoot 1.5 v area between the overshoot signal and vdd must be less than or equal to (see fgure below) 4.5 v-ns area between the undershoot signal and gnd must be less than or equal to (see fgure below) 4.5 v-ns o vershoot /u ndershoot s pecification for d ata , s trobe , and mask pins parameter max units peak amplitude allowed for overshoot 1.2 v peak amplitude allowed for undershoot 1.2 v area between the overshoot signal and vdd must be less than or equal to (see fgure below) 2.4 v-ns area between the undershoot signal and gnd must be less than or equal to (see fgure below) 2.4 v-ns address and control ac overshoot and undershoot defnition dq/dm/dqs ac overshoot and undershoot defnition ground v dd -3 -2 -1 +1 +2 +3 +4 +5 0 01 23 456 ti me (ns ) vo lt s (v ) undershoot overshoo t max .a m plitude =1 .5 v max. ar ea =4 .5 v- ns v dd -3 -2 -1 +1 +2 +3 +4 +5 0 01 23 456 vo lt s (v ) undershoot overshoot max. amplitude =1 .2 v ti me (ns) ground max. ar ea =2 .4 v- -n s
28 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f 32mx8 ordering information - vdd = 2.5v commercial range: 0c to +70c freq uency speed (ns) order part no. package 200 mhz 5 is43r83200f-5tl 66-pin tsop-ii, lead-free 166 mhz 6 is43r83200f-6tl 66-pin tsop-ii, lead-free industrial range: -40c to +85c f requency speed (ns) order part no. pack age 200 mhz 5 is43r83200f-5tli 66-pin tsop-ii, lead-free 166 mhz 6 is43r83200f-6tli 66-pin tsop-ii, lead-free
integrated silicon solution, inc. 29 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f 16mx16 ordering information - vdd = 2.5v commercial range: 0c to +70c freq uency speed (ns) order part no. package 200 mhz 5 IS43R16160F-5bl 60-ball fbga, lead-free IS43R16160F-5tl 66-pin tsop-ii, lead-free 166 mhz 6 IS43R16160F-6bl 60-ball fbga, lead-free IS43R16160F-6tl 66-pin tsop-ii, lead-free industrial range: -40c to +85c f requency speed (ns) order part no. pack age 200 mhz 5 IS43R16160F-5bli 60-ball fbga, lead-free IS43R16160F-5bi 60-ball fbga IS43R16160F-5tli 66-pin tsop-ii, lead-free 166 mhz 6 IS43R16160F-6bli 60-ball fbga, lead-free IS43R16160F-6bi 60-ball fbga IS43R16160F-6tli 66-pin tsop-ii, lead-free automotive (a1) range: -40c to +85c f requency speed (ns) order part no. pack age 200 mhz 5 is46r16160f-5bla1 60-ball fbga, lead-free is46r16160f-5tla1 66-pin tsop-ii, lead-free 166 mhz 6 is46r16160f-6bla1 60-ball fbga, lead-free is46r16160f-6tla1 66-pin tsop-ii, lead-free 8mx32 ordering information - vdd = 2.5v commercial range: 0c to +70c frequ ency speed (ns) order part no. package 200 mhz 5 is43r32800f-5bl 144-ball fbga, lead-free 166 mhz 6 is43r32800f-6bl 144-ball fbga, lead-free industrial range: -40c to +85c fre quency speed (ns) order part no. package 200 mhz 5 is43r32800f-5bli 144-ball fbga, lead-free is43r32800f-5bi 144-ball fbga 166 mhz 6 is43r32800f-6bli 144-ball fbga, lead-free automotive (a1) range: -40c to +85c fre quency speed (ns) order part no. package 166 mhz 6 is46r32800f-6bla1 144-ball fbga, lead-free automotive (a2) range: -40c to +105c f requency speed (ns) order part no. pack age 166 mhz 6 is46r16160f-6bla2 60-ball fbga, lead-free is46r16160f-6tla2 66-pin tsop-ii, lead-free
30 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f note : 4. formed leads shall be planar with respect to one another within 0.1mm 3. dimension b does not include dambar protrusion/intrusion. 2. dimension d and e1 do not include mold protrusion . at the seating plane after final test. 1. controlling dimension : mm package outline 10/04/2006
integrated silicon solution, inc. 31 rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f mini ball grid array package code: b (60-ball) 8mm x 13mm
32 integrated silicon solution, inc. rev. 0a 03/24/2014 is43r83200f is43/46r16160f, is43/46r32800f

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